Texas Instruments CC3235 SimpleLink Series - WDTTEST Register; WDTTEST Register Field Descriptions

WATCHDOG Registers www.ti.com
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SWRU543–January 2019
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Watchdog Timer
10.3.6 WDTTEST Register (offset = 418h) [reset = 0h]
WDTTEST is shown in Figure 10-7 and described in Table 10-7.
This register provides user-enabled stalling when the microcontroller asserts the CPU Halt flag during
debug.
Figure 10-7. WDTTEST Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED STALL
R-0h R/W-0h
7 6 5 4 3 2 1 0
RESERVED
R-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 10-7. WDTTEST Register Field Descriptions
Bit Field Type Reset Description
31-9 RESERVED R 0h
8 STALL R/W 0h
Watchdog Stall Enable
0h = The WDT continues counting if the microcontroller is stopped
with a debugger.
1h = If the microcontroller is stopped with a debugger, the watchdog
timer stops counting. Once the microcontroller is restarted, the
watchdog timer resumes counting.
7-0 RESERVED R 0h