Texas Instruments CC3235 SimpleLink Series - GPTMICR Register; GPTMICR Register Field Descriptions

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SWRU543–January 2019
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General-Purpose Timers
9.5.8 GPTMICR Register (offset = 24h) [reset = 0h]
Register mask: 0h
GPTMICR is shown in Figure 9-12 and described in Table 9-16.
This register clears the status bits in the GPTMRIS and GPTMMIS registers. Writing 1 to a bit clears the
corresponding bit in the GPTMRIS and GPTMMIS registers.
Figure 9-12. GPTMICR Register
31 30 29 28 27 26 25 24
RESERVED
R-X
23 22 21 20 19 18 17 16
RESERVED
R-X
15 14 13 12 11 10 9 8
RESERVED DMABINT RESERVED TBMCINT CBECINT CBMCINT TBTOCINT
R-X W1C-X R-X W1C-X W1C-X W1C-X W1C-X
7 6 5 4 3 2 1 0
RESERVED DMAAINT TAMCINT RESERVED CAECINT CAMCINT TATOCINT
R-X W1C-X W1C-X R-X W1C-X W1C-X W1C-X
Table 9-16. GPTMICR Register Field Descriptions
Bit Field Type Reset Description
31-14 RESERVED R X
13 DMABINT W1C X
GPTM Timer B DMA Done Interrupt Clear. Writing 1 to this bit clears
the DMABRIS bit in the GPTMRIS register and the DMABMIS bit in
the GPTMMIS register.
12 RESERVED R X
11 TBMCINT W1C X
GPTM Timer B Match Interrupt Clear. Writing 1 to this bit clears the
TBMRIS bit in the GPTMRIS register and the TBMMIS bit in the
GPTMMIS register.
10 CBECINT W1C X
GPTM Timer B Capture Mode Event Interrupt Clear. Writing 1 to this
bit clears the CBERIS bit in the GPTMRIS register and the CBEMIS
bit in the GPTMMIS register.
9 CBMCINT W1C X
GPTM Timer B Capture Mode Match Interrupt Clear. Writing 1 to this
bit clears the CBMRIS bit in the GPTMRIS register and the CBMMIS
bit in the GPTMMIS register.
8 TBTOCINT W1C X
GPTM Timer B Time-Out Interrupt Clear. Writing 1 to this bit clears
the TBTORIS bit in the GPTMRIS register and the TBTOMIS bit in
the GPTMMIS register.
7-6 RESERVED R X
5 DMAAINT W1C X
GPTM Timer A DMA Done Interrupt Clear. Writing 1 to this bit clears
the DMAARIS bit in the GPTMRIS register and the DMAAMIS bit in
the GPTMMIS register.
4 TAMCINT W1C X
GPTM Timer A Match Interrupt Clear. Writing 1 to this bit clears the
TAMRIS bit in the GPTMRIS register and the TAMMIS bit in the
GPTMMIS register.
3 RESERVED R X
2 CAECINT W1C X
GPTM Timer A Capture Mode Event Interrupt Clear. Writing 1 to this
bit clears the CAERIS bit in the GPTMRIS register and the CAEMIS
bit in the GPTMMIS register.
1 CAMCINT W1C X
GPTM Timer A Capture Mode Match Interrupt Clear. Writing 1 to this
bit clears the CAMRIS bit in the GPTMRIS register and the CAMMIS
bit in the GPTMMIS register.