AES Registers
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SWRU543–January 2019
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Advance Encryption Standard Accelerator (AES)
17.4.37 CRYPTOCLKEN Register (Offset = B8h) [reset = X]
CRYPTOCLKEN is shown in Figure 17-50 and described in Table 17-40.
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Physical address: 0x4402 50B8. CRYPTO_CLK_GATING
Figure 17-50. CRYPTOCLKEN Register
31 30 29 28 27 26 25 24
RESERVED
R-X
23 22 21 20 19 18 17 16
RESERVED
R-X
15 14 13 12 11 10 9 8
RESERVED
R-X
7 6 5 4 3 2 1 0
RESERVED RUNCLKEN
R-X R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 17-40. CRYPTOCLKEN Register Field Descriptions
Bit Field Type Reset Description
31-1 RESERVED R X
0 RUNCLKEN R/W 0h
CRYPTO_RUN_CLK_ENABLE:
0h = Enable the crypto clock during run
1h = Disable the crypto clock during run