Texas Instruments CC3235 SimpleLink Series - DMA_CHMAP2 Register

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SWRU543–January 2019
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Direct Memory Access (DMA)
4.3.4.21 DMA_CHMAP2 Register (offset = 518h) [reset = 0h]
DMA_CHMAP2 is shown in Figure 4-27 and described in Table 4-31.
Each 4-bit field of this register configures the DMA channel assignment.
Figure 4-27. DMA_CHMAP2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CH23SEL_n CH22SEL_n CH21SEL_n CH20SEL_n
R/W-0h R/W-0h R/W-0h R/W-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH19SEL_n CH18SEL_n CH17SEL_n CH16SEL_n
R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 4-31. DMA_CHMAP2 Register Field Descriptions
Bit Field Type Reset Description
31-28 CH23SEL_n R/W 0h
DMA channel 23 source select
27-24 CH22SEL_n R/W 0h
DMA channel 22 source select
23-20 CH21SEL_n R/W 0h
DMA channel 21 source select
19-16 CH20SEL_n R/W 0h
DMA channel 20 source select
15-12 CH19SEL_n R/W 0h
DMA channel 19 source select
11-8 CH18SEL_n R/W 0h
DMA channel 18 source select
7-4 CH17SEL_n R/W 0h
DMA channel 17 source select
3-0 CH16SEL_n R/W 0h
DMA channel 16 source select