Register Map
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SWRU543–January 2019
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Cortex
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-M4 Peripherals
3.3.1.8 UNPEND_0 to UNPEND_6 Register (offset = 280h to 298h) [reset = 0h]
UNPEND_0 to UNPEND_6 is shown in Figure 3-8 and described in Table 3-11.
The UNPENDn registers show which interrupts are pending and remove the pending state from interrupts.
Bit 0 of UNPEND0 corresponds to Interrupt 0; bit 31 corresponds to Interrupt 31. Bit 0 of UNPEND1
corresponds to Interrupt 32; bit 31 corresponds to Interrupt 63. Bit 0 of UNPEND2 corresponds to Interrupt
64; bit 31 corresponds to Interrupt 95. Bit 0 of UNPEND3 corresponds to Interrupt 96; bit 31 corresponds
to Interrupt 127. Bit 0 of UNPEND4 corresponds to Interrupt 128; bit 10 corresponds to Interrupt 159. Bit 0
of UNPEND5 corresponds to Interrupt 160; bit 31 corresponds to interrupt 191. Bit 0 of UNPEND6
corresponds to Interrupt 192; bit 7 corresponds to Interrupt 199.
NOTE: This register can only be accessed from privileged mode.
Figure 3-8. UNPEND_0 to UNPEND_6 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INT
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 3-11. UNPEND_0 to UNPEND_6 Register Field Descriptions
Bit Field Type Reset Description
31-0 INT R/W 0h
Interrupt Clear Pending
Setting a bit does not affect the active state of the corresponding
interrupt.
0h (W) = On a write, no effect.
0h (R) = On a read, indicates that the interrupt is not pending.
1h (W) = On a write, clears the corresponding INT[n] bit in the
PEND0 (for UNPEND0 to UNPEND3) register; PEND4 (for
UNPEND4) register; PEND5 (for UNPEND5) register; PEND6 (for
UNPEND6) register; so that interrupt [n] is no longer pending.
1h (R) = On a read, indicates that the interrupt is pending.
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