Texas Instruments CC3235 SimpleLink Series - GPT0 CLKCFG Register

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SWRU543–January 2019
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Power, Reset, and Clock Management
15.6.30 GPT0CLKCFG Register (offset = 90h) [reset = 0h]
GPT0CLKCFG is shown in Figure 15-33 and described in Table 15-33.
Figure 15-33. GPT0CLKCFG Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED DSLPCLKEN
R-0h R/W-0h
15 14 13 12 11 10 9 8
NU1 SLPCLKEN
R-0h R/W-0h
7 6 5 4 3 2 1 0
NU2 RUNCLKEN
R-0h R/W-0h
Table 15-33. GPT0CLKCFG Register Field Descriptions
Bit Field Type Reset Description
31-17 RESERVED R 0h
16 DSLPCLKEN R/W 0h
GPT_A0_DSLP_CLK_ENABLE
0h = Disable the GPT_A0 clock during deep-sleep
1h = Enable the GPT_A0 clock during deep-sleep
15-9 NU1 R 0h
8 SLPCLKEN R/W 0h
GPT_A0_SLP_CLK_ENABLE
0h = Disable the GPT_A0 clock during sleep
1h = Enable the GPT_A0 clock during sleep
7-1 NU2 R 0h
0 RUNCLKEN R/W 0h
GPT_A0_RUN_CLK_ENABLE
0h = Disable the GPT_A0 clock during run
1h = Enable the GPT_A0 clock during run