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ADC_MODULE Registers
471
SWRU543–January 2019
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Analog-to-Digital Converter (ADC)
13.4.1.11 ADC_TIMER_CONFIGURATION Register (offset = 68h) [reset = 111111h]
ADC_TIMER_CONFIGURATION is shown in Figure 13-13 and described in Table 13-13.
Figure 13-13. ADC_TIMER_CONFIGURATION Register
31 30 29 28 27 26 25 24
RESERVED TIMEREN TIMERRESET
R-0h R/W-0h R/W-0h
23 22 21 20 19 18 17 16
TIMERCOUNT
R/W-111111h
15 14 13 12 11 10 9 8
TIMERCOUNT
R/W-111111h
7 6 5 4 3 2 1 0
TIMERCOUNT
R/W-111111h
Table 13-13. ADC_TIMER_CONFIGURATION Register Field Descriptions
Bit Field Type Reset Description
31-26 RESERVED R 0h
25 TIMEREN R/W 0h
1h = Timer is enabled
24 TIMERRESET R/W 0h
1h = Reset timer
23-0 TIMERCOUNT R/W 111111h
Timer count configuration. 17-bit counter is supported. Other MSBs
are redundant.
13.4.1.12 ADC_TIMER_CURRENT_COUNT Register (offset = 70h) [reset = 0h]
ADC_TIMER_CURRENT_COUNT is shown in Figure 13-14 and described in Table 13-14.
Figure 13-14. ADC_TIMER_CURRENT_COUNT Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED TIMERCURRENTCOUNT
R-0h R-0h
Table 13-14. ADC_TIMER_CURRENT_COUNT Register Field Descriptions
Bit Field Type Reset Description
31-17 RESERVED R 0h
16-0 TIMERCURRENTCOUNT R 0h
Timer count configuration
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