I2S Registers
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SWRU543–January 2019
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Inter-Integrated Sound (I2S) Multichannel Audio Serial Port
12.5.20 ACLKXCTL Register (Offset = B0h) [reset = 60h]
ACLKXCTL is shown in Figure 12-23 and described in Table 12-25.
Return to Summary Table.
The transmit clock control register (ACLKXCTL) configures the transmit bit clock (ACLKX) and the transmit
clock generator.
Figure 12-23. ACLKXCTL Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
CLKXP ASYNC CLKXM CLKXDIV
R/W-0h R/W-1h R/W-1h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 12-25. ACLKXCTL Register Field Descriptions
Bit Field Type Reset Description
31-8 RESERVED R 0h
Reserved. The reserved bit location always returns the default value.
A value written to this field has no effect. If writing to this field,
always write the default value for future device compatibility.
7 CLKXP R/W 0h
Transmit bitstream clock polarity select bit.
0h = Reserved
1h = Falling edge. External receiver samples data on the rising edge
of the serial clock, so the transmitter must shift data out on the falling
edge of the serial clock.
6 ASYNC R/W 1h
Transmit/receive operation asynchronous enable bit.
0h = Synchronous. Transmit clock and frame sync provides the
source for both the transmit and receive sections. Note that in this
mode, the receive bit clock is an inverted version of the transmit bit
clock.
1h = Reserved
5 CLKXM R/W 1h
Transmit bit clock source bit.
0h = External transmit clock source from ACLKX pin.
1h = Internal transmit clock source from output of programmable bit
clock divider.
4-0 CLKXDIV R/W 0h
Transmit bit clock divide ratio bits determine the divide-down ratio
from AHCLKX to ACLKX.
0h = Divide-by-1
1h = Divide-by-2
2h - 1Fh = Divide-by-3 to divide-by-32
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