Texas Instruments CC3235 SimpleLink Series - UARTDMACTL Register

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SWRU543–January 2019
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Universal Asynchronous Receivers/Transmitters (UARTs)
6.3.13 UARTDMACTL Register (Offset = 48h) [reset = 0h]
UARTDMACTL is shown in Figure 6-15 and described in Table 6-15.
Return to Summary Table.
The UARTDMACTL register is the DMA control register.
Figure 6-15. UARTDMACTL Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED DMAERR TXDMAE RXDMAE
R-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 6-15. UARTDMACTL Register Field Descriptions
Bit Field Type Reset Description
31-3 RESERVED R 0h
2 DMAERR R/W 0h
DMA on Error
0h = DMA receive requests are unaffected when a receive error
occurs.
1h = DMA receive requests are automatically disabled when a
receive error occurs.
1 TXDMAE R/W 0h
Transmit DMA Enable
0h = DMA for the receive FIFO is disabled.
1h = DMA for the receive FIFO is enabled.
0 RXDMAE R/W 0h
Receive DMA Enable
0h = DMA for the receive FIFO is disabled.
1h = DMA for the receive FIFO is enabled.