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14
SWRU543–January 2019
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List of Figures
List of Figures
1-1. CC32xx MCU and Wi-Fi
®
System-on-Chip.............................................................................. 41
2-1. Application CPU Block Diagram.......................................................................................... 52
2-2. TPIU Block Diagram ....................................................................................................... 53
2-3. Cortex
®
-M4 Register Set .................................................................................................. 55
2-4. Data Storage................................................................................................................ 61
2-5. Vector Table ................................................................................................................ 66
2-6. Exception Stack Frame.................................................................................................... 68
2-7. Power-Management Architecture in CC32xx SoC..................................................................... 72
3-1. ACTLR Register ............................................................................................................ 84
3-2. STCTRL Register .......................................................................................................... 86
3-3. STRELOAD Register ...................................................................................................... 87
3-4. STCURRENT Register .................................................................................................... 88
3-5. EN_0 to EN_6 Register.................................................................................................... 89
3-6. DIS_0 to DIS_6 Register .................................................................................................. 90
3-7. PEND_0 to PEND_6 Register ............................................................................................ 91
3-8. UNPEND_0 to UNPEND_6 Register .................................................................................... 92
3-9. ACTIVE_0 to ACTIVE_6 Register........................................................................................ 93
3-10. PRI_0 to PRI_49 Register................................................................................................. 94
3-11. CPUID Register............................................................................................................. 95
3-12. INTCTRL Register.......................................................................................................... 96
3-13. VTABLE Register........................................................................................................... 98
3-14. APINT Register............................................................................................................. 99
3-15. SYSCTRL Register....................................................................................................... 101
3-16. CFGCTRL Register....................................................................................................... 102
3-17. SYSPRI1 Register ........................................................................................................ 104
3-18. SYSPRI2 Register ........................................................................................................ 105
3-19. SYSPRI3 Register ........................................................................................................ 106
3-20. SYSHNDCTRL Register ................................................................................................. 107
3-21. FAULTSTAT Register.................................................................................................... 110
3-22. HFAULTSTAT Register .................................................................................................. 114
3-23. FAULTDDR Register ..................................................................................................... 115
3-24. SWTRIG Register......................................................................................................... 116
4-1. Ping-Pong Mode .......................................................................................................... 123
4-2. Memory Scatter-Gather Mode .......................................................................................... 124
4-3. Peripheral Scatter-Gather Mode........................................................................................ 125
4-4. DMA_SRCENDP Register............................................................................................... 129
4-5. DMA_DSTENDP Register ............................................................................................... 129
4-6. DMA_CHCTL Register................................................................................................... 130
4-7. DMA_STAT Register ..................................................................................................... 133
4-8. DMA_CFG Register ...................................................................................................... 134
4-9. DMA_CTLBASE Register................................................................................................ 135
4-10. DMA_ALTBASE Register................................................................................................ 136
4-11. DMA_WAITSTAT Register .............................................................................................. 137
4-12. DMA_SWREQ Register.................................................................................................. 138
4-13. DMA_USEBURSTSET Register ........................................................................................ 139
4-14. DMA_USEBURSTCLR Register........................................................................................ 140
4-15. DMA_REQMASKSET Register ......................................................................................... 141