Texas Instruments CC3235 SimpleLink Series - Page 13

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13
SWRU543–January 2019
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Contents
20.3.2 CRCSEED Register (Offset = C10h) [reset = 0h] .......................................................... 759
20.3.3 CRCDIN Register (Offset = C14h) [reset = 0h]............................................................. 760
20.3.4 CRCRSLTPP Register (Offset = C18h) [reset = 0h] ....................................................... 761
21 On-Chip Parallel Flash....................................................................................................... 762
21.1 Flash Memory Configuration ............................................................................................ 763
21.2 Interrupts................................................................................................................... 763
21.3 Flash Memory Programming ............................................................................................ 763
21.4 32-Word Flash Memory Write Buffer................................................................................... 764
21.5 Flash Registers ........................................................................................................... 765
21.5.1 FMA Register (Offset = 0h) [reset = 0h] ..................................................................... 766
21.5.2 FMD Register (Offset = 4h) [reset = 0h] ..................................................................... 767
21.5.3 FMC Register (Offset = 8h) [reset = 0h] ..................................................................... 768
21.5.4 FCRIS Register (Offset = Ch) [reset = 0h] .................................................................. 770
21.5.5 FCIM Register (offset = 10h) [reset = 0h] ................................................................... 772
21.5.6 FCMISC Register (Offset = 14h) [reset = 0h] ............................................................... 773
21.5.7 FMC2 Register (Offset = 20h) [reset = 0h] .................................................................. 775
21.5.8 FWBVAL Register (Offset = 30h) [reset = 0h] .............................................................. 776
21.5.9 FWBn Register (Offset = 100h) [reset = 0h] ................................................................ 777
21.6 CC3235SF Boot Flow .................................................................................................... 778
21.7 Flash User Application and Memory Partition......................................................................... 778
21.8 Programming, Bootstrapping, and Updating the Flash User Application.......................................... 780
21.9 Image Authentication and Integrity Check............................................................................. 781
21.10 Debugging Flash User Application Using JTAG...................................................................... 783
A Software Development Kit Examples................................................................................... 784
B CC3235x Device Miscellaneous Registers............................................................................ 785
B.1 DMA_IMR Register (offset = 8Ch) [reset = FF0Fh] .................................................................. 786
B.2 DMA_IMS Register (offset = 90h) [reset = 0h]........................................................................ 788
B.3 DMA_IMC Register (offset = 94h) [reset = 0h]........................................................................ 790
B.4 DMA_ICR Register (offset = 9Ch) [reset = 0h] ....................................................................... 792
B.5 DMA_MIS Register (offset = A0h) [reset = 0h] ....................................................................... 794
B.6 DMA_RIS Register (offset = A4h) [reset = 0h]........................................................................ 796
B.7 GPTTRIGSEL Register (offset = B0h) [reset = 0h]................................................................... 798