Texas Instruments CC3235 SimpleLink Series - CC_IRQSTATUS Register; Cc_Irqstatus

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SWRU543–January 2019
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Parallel Camera Interface Module
14.6.3 CC_IRQSTATUS Register (Offset = 18h) [reset = 0h]
CC_IRQSTATUS is shown in Figure 14-11 and described in Table 14-6.
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The interrupt status regroups all the status of the module internal events that can generate an interrupt
(CCP and parallel mode)
Figure 14-11. CC_IRQSTATUS Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED FS_IRQ LE_IRQ LS_IRQ FE_IRQ
R-0h R/W-0h R/W-0h R/W-0h R/W-0h
15 14 13 12 11 10 9 8
RESERVED FSP_ERR-IRQ FW_ERR_IRQ FSC_ERR_IRQ SSC_ERR_IRQ
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
RESERVED FIFO_NOEMPT
Y_IRQ
FIFO_FULL_IR
Q
FIFO_THR_IR
Q
FIFO_OF_IRQ FIFO_UF_IRQ
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 14-6. CC_IRQSTATUS Register Field Descriptions
Bit Field Type Reset Description
31-20 RESERVED R 0h
19 FS_IRQ R/W 0h
Frame Start has occurred
0h (W) = Event status bit unchanged
0h (R) = Event false
1h (W) = Event status bit is reset
1h (R) = Event is true ("pending")
18 LE_IRQ R/W 0h
Line End has occurred
0h (W) = Event status bit unchanged
0h (R) = Event false
1h (W) = Event status bit is reset
1h (R) = Event is true ("pending")
17 LS_IRQ R/W 0h
Line Start has occurred
0h (W) = Event status bit unchanged
0h (R) = Event false
1h (W) = Event status bit is reset
1h (R) = Event is true ("pending")
16 FE_IRQ R/W 0h
Frame End has occurred
0h (W) = Event status bit unchanged
0h (R) = Event false
1h (W) = Event status bit is reset
1h (R) = Event is true ("pending")
15-12 RESERVED R/W 0h
11 FSP_ERR-IRQ R/W 0h
FSP code error
0h (W) = Event status bit unchanged
0h (R) = Event false
1h (W) = Event status bit is reset
1h (R) = Event is true ("pending")