ACTIVE (RUN)
HIBERNATE
(HIB)
LOW-POWER
DEEP-SLEEP
(LPDS)
CC3235 APPs Processor
Current Consumption: ~700 µA (Idle connected mode)
Clock: 32.768 kHz
RAM retention: No (default)(API to be invoked to retain specific colums of RAM)
CPU Context Retention: No (default) (Context need to be saved and restoed in SW)
Peripheral context retention: No (default) (Context need to be saved and restored in SE or
reconfigure peripheral on wakeup in SE)
Wake Source: GPIO (2,4,11,13,17,24 ±any 1 only), Wake Timer, Network Wakeup
Current Consumption: ~4 µA
Clock: 32.768 kHz
RAM retention: No (default)
CPU Context Retention: No (default)
Peripheral context retention: No (default)
Wake Source: GPIO (2,4,11,13,17,24), Slow Clock Counter
CC3235 subsystem
CURRENT CONSUMPTION
WAKEUP TIME
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Power Management Control Architecture
519
SWRU543–January 2019
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Power, Reset, and Clock Management
– Once a brownout condition is detected, the application software may choose to enter hibernate
mode to prevent further oscillatory brownouts that may cause unpredictable system behavior and
possible damage to the end equipment. The system can subsequently be made to restart on an
RTC timer, on a chip reset, or on plugging of new batteries.
• Shutdown mode:
– 32.768-KHz is in off mode
– Complete wake from cold boot
– Very low leakage current of about 1 µA
– Recommended to be used when radio activity is low and the device can be in off mode in between
For CC32xx applications where battery life is critical, maximize the fraction of time spent in LPDS or HIB
modes compared to active mode and other sleep modes.
Figure 15-2. Sleep Modes
15.2 Power Management Control Architecture
The CC32xx Wi-Fi microcontroller is a multiprocessor system-on-chip with several subsystems
independently cycling between active and sleep states (application processor, network processor, WLAN-
MAC, and WLAN-PHY) for optimal energy use. The activities of various subsystems are tied to the data
and management traffic. In absence of events and traffic, all the systems are typically in a sleep state
(LPDS).
The timing of sleep and wakeup do not need to be synchronized across subsystems. For example, in an
idle-connected case, when the association to the AP is maintained most of the time, the WLAN subsystem
is in LPDS and wakes up periodically for short intervals, only to listen for any incoming beacon packets
and delivery pending messages from the AP (apart from occasional keep alive packet transmissions).
While this repeats in multiples of the beacon period (104 mS), the application processor may implement its
own sleep strategy with a different periodicity.
An advanced power management scheme has been implemented at the CC32xx chip level. This scheme
handles the asynchronous sleep-wake requirements of multiple processors and Wi-Fi radio subsystems in
a way that is transparent to the software, yet energy efficient.
The chip-level power-management scheme is such that the application program is unaware of the power
state transitions of the other subsystems. This approach insulates the user from the real-time complexities
of a multiprocessor system; it improves robustness by eliminating race conditions and simplifies the
application development process.
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