UART Registers
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SWRU543–January 2019
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Universal Asynchronous Receivers/Transmitters (UARTs)
6.3.10 UARTRIS Register (Offset = 3Ch) [reset = 0h]
UARTRIS is shown in Figure 6-12 and described in Table 6-12.
Return to Summary Table.
The UARTRIS register is the raw interrupt status register. On a read, this register gives the current raw
status value of the corresponding interrupt. A write has no effect.
Figure 6-12. UARTRIS Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED DMATXRIS DMARXRIS
R-0h R-0h R-0h
15 14 13 12 11 10 9 8
RESERVED RESERVED OERIS BERIS PERIS
R-0h R-0h R-0h R-0h R-0h
7 6 5 4 3 2 1 0
FERIS RTRIS TXRIS RXRIS DSRRIS DCDRIS CTSRIS RIRIS
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 6-12. UARTRIS Register Field Descriptions
Bit Field Type Reset Description
31-18 RESERVED R 0h
17 DMATXRIS R 0h
Transmit DMA Raw Interrupt Status
This bit is cleared by writing a 1 to the DMATXIC bit in the UARTICR
register.
0h = No interrupt
1h = The transmit DMA has completed.
16 DMARXRIS R 0h
Receive DMA Raw Interrupt Status
This bit is cleared by writing a 1 to the DMARXIC bit in the UARTICR
register.
0h = No interrupt
1h = The receive DMA has completed.
15-11 RESERVED R 0h
10 OERIS R 0h
UART Overrun Error Raw Interrupt Status
This bit is cleared by writing a 1 to the OEIC bit in the UARTICR
register.
0h = No interrupt
1h = An overrun error has occurred.
9 BERIS R 0h
UART Break Error Raw Interrupt Status
This bit is cleared by writing a 1 to the BEIC bit in the UARTICR
register.
0h = No interrupt
1h = A break error has occurred.
8 PERIS R 0h
UART Parity Error Raw Interrupt Status
This bit is cleared by writing a 1 to the PEIC bit in the UARTICR
register.
0h = No interrupt
1h = A parity error has occurred.
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