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UART Registers
197
SWRU543–January 2019
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Universal Asynchronous Receivers/Transmitters (UARTs)
Table 6-12. UARTRIS Register Field Descriptions (continued)
Bit Field Type Reset Description
7 FERIS R 0h
UART Framing Error Raw Interrupt Status
This bit is cleared by writing a 1 to the FEIC bit in the UARTICR
register.
0h = No interrupt
1h = A framing error has occurred.
6 RTRIS R 0h
UART Receive Time-Out Raw Interrupt Status
This bit is cleared by writing a 1 to the RTIC bit in the UARTICR
register.
0h = No interrupt
1h = A receive time out has occurred.
5 TXRIS R 0h
UART Transmit Raw Interrupt Status
If the EOT bit is set, the last bit of all transmitted data and flags has
left the serializer. This bit is cleared by writing a 1 to the TXIC bit in
the UARTICR register or by writing data to the transmit FIFO until it
becomes greater than the trigger level, if the FIFO is enabled, or by
writing a single byte if the FIFO is disabled.
0h = No interrupt
1h = If the EOT bit in the UARTCTL register is clear, the transmit
FIFO level has passed through the condition defined in the
UARTIFLS register.
4 RXRIS R 0h
UART Receive Raw Interrupt Status
This bit is cleared by writing a 1 to the RXIC bit in the UARTICR
register or by reading data from the receive FIFO until it becomes
less than the trigger level, if the FIFO is enabled, or by reading a
single byte if the FIFO is disabled.
0h = No interrupt
1h = The receive FIFO level has passed through the condition
defined in the UARTIFLS register.
3 DSRRIS R 0h
Reserved
2 DCDRIS R 0h
Reserved
1 CTSRIS R 0h
UART Clear to Send Modem Raw Interrupt Status
This bit is cleared by writing a 1 to the CTSIC bit in the UARTICR
register.
0h = No interrupt
1h = Clear to Send used for software flow control.
0 RIRIS R 0h
Reserved
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