Texas Instruments CC3235 SimpleLink Series - Power-Management Architecture in Cc32 Xx Soc

I/O Mux
Cortex-M4
Dedicated Application Processor
ROM
(Boot, Drivers)
SRAM
(Code, Data)
Watchdog
Timer
Peripheral
N
Peripheral
1
clk
rst
clk
rst
clk
rst
ARCM
Application Reset & Clock Control
FCLK
HCLK
External
SPI Flash
Network Processor
HWA
Cortex-M3 DMA ROM RAM
HWA
HWA
802.11bgna MAC
HWA
Cortex-M3 DMA ROM RAM
HWA
HWA
802.11bgna MAC
Cortex-M3 DMA
Cortex-M3 DMA
802.11 bgna Radio
Global Power Reset-Clock Controller
(GPRCM)
SYSRESETn
SYSTRESETREQ
Clocks
SW Register I/F
Sleep Status
Sleeping, Deepslieep
App Reset
On-Chip PMU
(Power Management Unit)
Hibernate
Controller
RTC
Counter
Pad
Wakeup
32.768 KHz
LF-XOSC
40 MHz
HF-XOSC
PLL
240 MHz
I/O Pads
Interconnect
Interconnect
6LPSOH/LQNŒ6XEV\VWHP
6LPSOH/LQNŒ
API Call I/F
IRQ IRQ IRQ
Internal Supply Rails
Application Microcontroller Subsystem
SW Register I/F
Functional Description www.ti.com
72
SWRU543–January 2019
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Cortex
®
-M4 Processor
Figure 2-7. Power-Management Architecture in CC32xx SoC