AES Registers
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SWRU543–January 2019
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Advance Encryption Standard Accelerator (AES)
17.4.41 DTHE_AES_IC Register (Offset = 82Ch) [reset = X]
DTHE_AES_IC is shown in Figure 17-54 and described in Table 17-44.
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Figure 17-54. DTHE_AES_IC Register
31 30 29 28 27 26 25 24
RESERVED
R-X
23 22 21 20 19 18 17 16
RESERVED
R-X
15 14 13 12 11 10 9 8
RESERVED
R-X
7 6 5 4 3 2 1 0
RESERVED Dout Din Cout Cin
R-X WC-0h WC-0h WC-0h WC-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 17-44. DTHE_AES_IC Register Field Descriptions
Bit Field Type Reset Description
31-4 RESERVED R X
3 Dout WC 0h
Clear “output data movement done” flag
2 Din WC 0h
Clear “input data movement done” flag
1 Cout WC 0h
Clear “context output done” flag
0 Cin WC 0h
Clear “context input done” flag
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