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Camera Registers
505
SWRU543–January 2019
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Parallel Camera Interface Module
14.6.6 CC_CTRL_DMA Register (Offset = 44h) [reset = 207h]
CC_CTRL_DMA is shown in Figure 14-14 and described in Table 14-9.
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This register controls the DMA interface of the camera core block (CCP and parallel mode).
Figure 14-14. CC_CTRL_DMA Register
31 30 29 28 27 26 25 24
RESERVED
R/W-1h
23 22 21 20 19 18 17 16
RESERVED
R/W-1h
15 14 13 12 11 10 9 8
RESERVED DMA_EN
R/W-1h R/W-0h
7 6 5 4 3 2 1 0
RESERVED FIFO_THRESHOLD
R/W-0h R/W-7h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 14-9. CC_CTRL_DMA Register Field Descriptions
Bit Field Type Reset Description
31-9 RESERVED R/W 1h
8 DMA1_DISABLE R/W 0h
DMA1 disable capability. Only use DMA0 (threshold-based).
0h = DMA1 line can be activated
1h = DMA1 line can not be activated
8 DMA_EN R/W 0h
Sets the number of DMA request lines.
0h = DMA interface disabled. The DMA request line stays inactive.
1h = DMA interface enabled. The DMA request line is operational.
7 RESERVED R/W 0h
6-0 FIFO_THRESHOLD R/W 7h
Sets the threshold of the FIFO. The assertion of the DMA request
line takes place when the threshold is reached.
00000000h = Threshold set to 1
00000001h = Threshold set to 2
...
01111111h = Threshold set to 128
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