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Functional Description
313
SWRU543–January 2019
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Copyright © 2019, Texas Instruments Incorporated
General-Purpose Timers
When operating in edge-time mode, the counter uses a modulo 2
24
count if prescaler is enabled, or 216 if
not. If there is a possibility the edge could take longer than the count, then another timer configured in
periodic-timer mode can be implemented to ensure detection of the missed edge. The periodic timer
should be configured in such a way that:
• The periodic timer cycles at the same rate as the edge-time timer.
• The periodic timer interrupt has a higher interrupt priority than the edge-time time-out interrupt.
• If the periodic timer ISR is entered, software must check if an edge-time interrupt is pending and if it is,
the value of the counter must be subtracted by 1 before being used to calculate the snapshot time of
the event.
9.3.2.4 PWM Mode
The GPTM supports a simple PWM generation mode. In PWM mode, the timer is configured as a 24-bit
down counter with a start value (and thus period) defined by the GPTMTnILR and GPTMTnPR registers.
In this mode, the PWM frequency and period are synchronous events, and therefore ensured to be glitch-
free. PWM mode is enabled in the GPTMTnMR register by setting the TnAMS bit to 0x1, the TnCMR bit to
0x0, and the TnMR field to 0x2. Table 9-7 lists the values loaded into the timer registers when the timer is
enabled.
Table 9-7. Counter Values When the Timer is Enabled in PWM Mode
Register Count-Down Mode Count-Up Mode
GPTMTnR GPTMTnILR Not available
GPTMTnV GPTMTnILR Not available
When software writes the TnEN bit in the GPTMCTL register, the counter begins counting down until it
reaches the 0x0 state. On the next counter cycle in periodic mode, the counter reloads its start value from
the GPTMTnILR and GPTMTnPR registers, and continues counting until disabled by software clearing the
TnEN bit in the GPTMCTL register. The timer can generate interrupts based on three types of events:
rising edge, falling edge, or both. The event is configured by the TnEVENT field of the GPTMCTL register,
and the interrupt is enabled by setting the TnPWMIE bit in the GPTMTnMR register. When the event
occurs, the CnERIS bit is set in the GPTM Raw Interrupt Status (GPTMRIS) register, and is held until it is
cleared by writing the GPTM Interrupt Clear (GPTMICR) register. If the capture mode event interrupt is
enabled in the GPTM Interrupt Mask (GPTMIMR) register, the GPTM also sets the CnEMIS bit in the
GPTM Masked Interrupt Status (GPTMMIS) register. The interrupt status bits are not updated unless the
TnPWMIE bit is set.
In addition, when the TnPWMIE bit is set and a capture event occurs, the timer automatically generates
triggers to the DMA if the trigger capability is enabled, by setting the TnOTE bit in the GPTMCTL register
and the CnEDMAEN bit in the GPTMDMAEV register.
In this mode, the GPTMTnR and GPTMTnV registers always have the same value.
The output PWM signal asserts when the counter is at the value of the GPTMTnILR and GPTMTnPR
registers (its start state), and is deasserted when the counter value equals the value in the
GPTMTnMATCHR and GPTMTnPMR registers. Software can invert the output PWM signal by setting the
TnPWML bit in the GPTMCTL register.
NOTE: If PWM output inversion is enabled, edge-detection interrupt behavior is reversed. Thus, if a
positive-edge interrupt trigger has been set and the PWM inversion generates a positive
edge, no event-trigger interrupt asserts. Instead, the interrupt is generated on the negative
edge of the PWM signal.
Figure 9-4 shows how to generate an output PWM with a 1-ms period and a 66% duty cycle assuming a
50-MHz input clock and TnPWML = 0 (duty cycle would be 33% for the TnPWML = 1 configuration). For
this example, the start value is GPTMTnILR=0xC350, and the match value is GPTMTnMATCHR=0x411A.
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