Texas Instruments CC3235 SimpleLink Series - UARTICR Register; UARTICR Register Field Descriptions

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SWRU543–January 2019
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Universal Asynchronous Receivers/Transmitters (UARTs)
6.3.12 UARTICR Register (Offset = 44h) [reset = 0h]
UARTICR is shown in Figure 6-14 and described in Table 6-14.
Return to Summary Table.
The UARTICR register is the interrupt clear register. On a write of 1, the corresponding interrupt (both raw
interrupt and masked interrupt, if enabled) is cleared. A write of 0 has no effect.
Figure 6-14. UARTICR Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED DMATXIC DMARXIC
R-0h W1C-0h W1C-0h
15 14 13 12 11 10 9 8
RESERVED RESERVED OEIC BEIC PEIC
R-0h W1C-0h W1C-0h W1C-0h W1C-0h
7 6 5 4 3 2 1 0
FEIC RTIC TXIC RXIC DSRMIC DCDMIC CTSMIC RIMIC
W1C-0h W1C-0h W1C-0h W1C-0h W1C-0h W1C-0h W1C-0h W1C-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 6-14. UARTICR Register Field Descriptions
Bit Field Type Reset Description
31-18 RESERVED R 0h
17 DMATXIC W1C 0h
Transmit DMA Interrupt Clear
Writing a 1 to this bit clears the DMATXRIS bit in the UARTRIS
register and the DMATXMIS bit in the UARTMIS register.
16 DMARXIC W1C 0h
Receive DMA Interrupt Clear
Writing a 1 to this bit clears the DMARXRIS bit in the UARTRIS
register and the DMARXMIS bit in the UARTMIS register.
15-11 RESERVED R 0h
10 OEIC W1C 0h
Overrun Error Interrupt Clear
Writing a 1 to this bit clears the OERIS bit in the UARTRIS register
and the OEMIS bit in the UARTMIS register.
9 BEIC W1C 0h
Break Error Interrupt Clear
Writing a 1 to this bit clears the BERIS bit in the UARTRIS register
and the BEMIS bit in the UARTMIS register.
8 PEIC W1C 0h
Parity Error Interrupt Clear
Writing a 1 to this bit clears the PERIS bit in the UARTRIS register
and the PEMIS bit in the UARTMIS register.
7 FEIC W1C 0h
Framing Error Interrupt Clear
Writing a 1 to this bit clears the FERIS bit in the UARTRIS register
and the FEMIS bit in the UARTMIS register.
6 RTIC W1C 0h
Receive Time-Out Interrupt Clear
Writing a 1 to this bit clears the RTRIS bit in the UARTRIS register
and the RTMIS bit in the UARTMIS register.
5 TXIC W1C 0h
Receive Time-Out Interrupt Clear
Writing a 1 to this bit clears the RTRIS bit in the UARTRIS register
and the RTMIS bit in the UARTMIS register.
4 RXIC W1C 0h
Receive Interrupt Clear
Writing a 1 to this bit clears the RXRIS bit in the UARTRIS register
and the RXMIS bit in the UARTMIS register.