Timer Registers
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SWRU543–January 2019
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General-Purpose Timers
9.5.12 GPTMTBMATCHR Register (offset = 34h) [reset = FFFFh]
GPTMTBMATCHR is shown in Figure 9-16 and described in Table 9-20.
When a GPTM is configured to one of the 32-bit modes, the contents of bits 15:0 in this register are
loaded into the upper 16 bits of the GPTMTAMATCHR register. Reads from this register return the current
match value of Timer B, and writes are ignored. In a 16-bit mode, bits 15:0 are used for the match value.
Bits 31:16 are reserved in both cases.
Figure 9-16. GPTMTBMATCHR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TBMR
R/W-FFFFh
Table 9-20. GPTMTBMATCHR Register Field Descriptions
Bit Field Type Reset Description
31-0 TBMR R/W FFFFh
GPTM Timer B Match Register. This value is compared to the
GPTMTBR register to determine match events.
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