SPI Registers
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SWRU543–January 2019
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SPI (Serial Peripheral Interface)
8.6.7 SPI_CHSTAT Register (offset = 130h) [reset = 0h]
SPI_CHSTAT is shown in Figure 8-26 and described in Table 8-13.
This register provides status information about the transmitter and receiver registers of the channel.
Figure 8-26. SPI_CHSTAT Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED RXFFF RXFFE TXFFF TXFFE EOT TXS RXS
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 8-13. SPI_CHSTAT Register Field Descriptions
Bit Field Type Reset Description
31-7 RESERVED R 0h
6 RXFFF R 0h
Channel FIFO receive buffer full status
0h (R) = FIFO receive buffer is not full
1h (R) = FIFO receive buffer is full
5 RXFFE R 0h
Channel FIFO receive buffer empty status
0h (R) = FIFO receive buffer is not empty
1h (R) = FIFO receive buffer is empty
4 TXFFF R 0h
Channel FIFO transmit buffer full status
0h (R) = FIFO transmit buffer is not full
1h (R) = FIFO transmit buffer is full
3 TXFFE R 0h
Channel FIFO transmit buffer empty status
0h (R) = FIFO transmit buffer is not empty
1h (R) = FIFO transmit buffer is empty
2 EOT R 0h Channel end of transfer status.
The definitions of beginning and end of transfer vary with master
versus slave and the transfer format (turbo mode).
See dedicated chapters for details.
0h (R) = This flag is automatically cleared when the shift register is
loaded with the data from the transmitter register (beginning of
transfer).
1h (R) = This flag is automatically set to one at the end of a SPI
transfer.
1 TXS R 0h
Channel transmitter register status
0h (R) = Register is full
1h (R) = Register is empty
0 RXS R 0h
Channel receiver register status
0h (R) = Register is empty
1h (R) = Register is full
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