SD-HOST Registers
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SWRU543–January 2019
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SD Host Controller Interface
11.7.7 MMCHS_RSP32 Register (Offset = 214h) [reset = 0h]
Command Response[63:32] register
MMCHS_RSP32 is shown in Figure 11-8 and described in Table 11-11.
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This 32-bit register holds bits positions [63:32] of command response type R2.
Figure 11-8. MMCHS_RSP32 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSP3 RSP2
R-0h R-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 11-11. MMCHS_RSP32 Register Field Descriptions
Bit Field Type Reset Description
31-16 RSP3 R 0h
R2: Command Response [63:48]
15-0 RSP2 R 0h
R2: Command Response [47:32]
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