Texas Instruments CC3235 SimpleLink Series - DMA_CHMAP3 Register

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154
SWRU543–January 2019
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Direct Memory Access (DMA)
4.3.4.22 DMA_CHMAP3 Register (offset = 51Ch) [reset = 0h]
DMA_CHMAP3 is shown in Figure 4-28 and described in Table 4-32.
Each 4-bit field of this register configures the DMA channel assignment.
Figure 4-28. DMA_CHMAP3 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CH31SEL_n CH30SEL_n CH29SEL_n CH28SEL_n
R/W-0h R/W-0h R/W-0h R/W-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH27SEL_n CH26SEL_n CH25SEL_n CH24SEL_n
R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 4-32. DMA_CHMAP3 Register Field Descriptions
Bit Field Type Reset Description
31-28 CH31SEL_n R/W 0h
DMA channel 31 source select
27-24 CH30SEL_n R/W 0h
DMA channel 30 source select
23-20 CH29SEL_n R/W 0h
DMA channel 29 source select
19-16 CH28SEL_n R/W 0h
DMA channel 28 source select
15-12 CH27SEL_n R/W 0h
DMA channel 27 source select
11-8 CH26SEL_n R/W 0h
DMA channel 26 source select
7-4 CH25SEL_n R/W 0h
DMA channel 25 source select
3-0 CH24SEL_n R/W 0h
DMA channel 24 source select