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AES Registers
659
SWRU543–January 2019
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Advance Encryption Standard Accelerator (AES)
17.4.38 DTHE_AES_IM Register (Offset = 820h) [reset = X]
DTHE_AES_IM is shown in Figure 17-51 and described in Table 17-41.
Return to Summary Table.
The interrupt mask set register controls which interrupt source interrupts the processor.
Figure 17-51. DTHE_AES_IM Register
31 30 29 28 27 26 25 24
RESERVED
R-X
23 22 21 20 19 18 17 16
RESERVED
R-X
15 14 13 12 11 10 9 8
RESERVED
R-X
7 6 5 4 3 2 1 0
RESERVED Dout Din Cout Cin
R-X R/W-1h R/W-1h R/W-1h R/W-1h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 17-41. DTHE_AES_IM Register Field Descriptions
Bit Field Type Reset Description
31-4 RESERVED R X
3 Dout R/W 1h
Data out: This interrupt is raised when DMA finishes writing last word
of the process result.
2 Din R/W 1h
Data in: This interrupt is raised when DMA writes last word of input
data to internal FIFO of the engine.
1 Cout R/W 1h
Context out: This interrupt is raised when DMA completes the output
context movement from internal register.
0 Cin R/W 1h
Context in: This interrupt is raised when DMA completes context
write to internal register.
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