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I2S Registers
443
SWRU543–January 2019
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Inter-Integrated Sound (I2S) Multichannel Audio Serial Port
12.5.19 AFSXCTL Register (Offset = ACh) [reset = 0h]
AFSXCTL is shown in Figure 12-22 and described in Table 12-24.
Return to Summary Table.
The transmit frame sync control register (AFSXCTL) configures the transmit frame sync (AFSX).
Figure 12-22. AFSXCTL Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
XMOD
R/W-0h
7 6 5 4 3 2 1 0
XMOD RESERVED FXWID RESERVED FSXM FSXP
R/W-0h R-0h R/W-0h R-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 12-24. AFSXCTL Register Field Descriptions
Bit Field Type Reset Description
31-16 RESERVED R 0h
Reserved. The reserved bit location always returns the default value.
A value written to this field has no effect. If writing to this field,
always write the default value for future device compatibility.
15-7 XMOD R/W 0h
Transmit frame sync mode select bits.
0h = Reserved
1h = Reserved
2h-20h = 2-slot TDM (I2S mode)
180h - 1FFh = Reserved
6-5 RESERVED R 0h
Reserved. The reserved bit location always returns the default value.
A value written to this field has no effect. If writing to this field,
always write the default value for future device compatibility.
4 FXWID R/W 0h
Transmit frame sync width select bit indicates the width of the
transmit frame sync (AFSX) during its active period.
0h = Reserved
1h = Single word
3-2 RESERVED R 0h
Reserved. The reserved bit location always returns the default value.
A value written to this field has no effect. If writing to this field,
always write the default value for future device compatibility.
1 FSXM R/W 0h
Transmit frame sync generation select bit.
0h = Externally-generated transmit frame sync
1h = Internally-generated transmit frame sync
0 FSXP R/W 0h
Transmit frame sync polarity select bit.
0h = Reserved
1h = A falling edge on transmit frame sync (AFSX) indicates the
beginning of a frame.