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SWRU543–January 2019
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Cortex
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-M4 Peripherals
3.3.1.18 SYSPRI2 Register (Offset = D1Ch) [reset = 0h]
SYSPRI2 is shown in Figure 3-18 and described in Table 3-21.
Return to Summary Table.
The SYSPRI2 register configures the priority level, 0 to 7 of the SVCall handler. This register is byte-
accessible.
NOTE: This register can only be accessed from privileged mode.
Figure 3-18. SYSPRI2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SVC RESERVED
R/W-0h R-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 3-21. SYSPRI2 Register Field Descriptions
Bit Field Type Reset Description
31-29 SVC R/W 0h
SVCall Priority
This field configures the priority level of SVCall. Configurable priority
values are in the range 0-7, with lower values having higher priority.
28-0 RESERVED R 0h
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