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Texas Instruments CC3235 SimpleLink Series - SPI_CHCONF Register

Texas Instruments CC3235 SimpleLink Series
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SPI Registers
297
SWRU543–January 2019
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Copyright © 2019, Texas Instruments Incorporated
SPI (Serial Peripheral Interface)
8.6.6 SPI_CHCONF Register (offset = 12Ch) [reset = 60000h]
SPI_CHCONF is shown in Figure 8-25 and described in Table 8-12.
This register is dedicated to the configuration of the channel. The following table lists the allowed data line
configurations per channel. The user must program which data line to use and in which direction (receive
or transmit), according to the single data pin or 2-pin interface mode shared with the external slave or
master device.
IS DPE1 DPE0 TRM (Transmit and Receive)
0 0 0 Supported
0 0 1 Supported
0 1 0 Supported
0 1 1 Not supported (unpredictable result)
1 0 0 Supported
1 0 1 Supported
1 1 0 Supported
1 1 1 Not supported (unpredictable result)
Figure 8-25. SPI_CHCONF Register
31 30 29 28 27 26 25 24
RESERVED CLKG FFER FFEW RESERVED
R-0h R/W-0h R/W-0h R/W-0h R-0h
23 22 21 20 19 18 17 16
RESERVED FORCE TURBO IS DPE1 DPE0
R-0h R/W-0h R/W-0h R/W-1h R/W-1h R/W-0h
15 14 13 12 11 10 9 8
DMAR DMARW TRM WL
R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
WL EPOL CLKD POL PHA
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 8-12. SPI_CHCONF Register Field Descriptions
Bit Field Type Reset Description
31-30 RESERVED R 0h
29 CLKG R/W 0h Clock divider granularity.
This register defines the granularity of channel clock divider: power
of two or one clock cycle granularity.
When this bit is set the register SPI_CHCTRL[EXTCLK] must be
configured to reach a maximum of 4096 clock divider ratio.
Then the clock divider ratio is a concatenation of
SPI_CHCONF[CLKD] and SPI_CHCTRL[EXTCLK] values
0h = Clock granularity of power of two
1h = One clock cycle granularity
28 FFER R/W 0h
FIFO enabled for receive: Only one channel can have this bit field
set.
0h = The buffer is not used to receive data.
1h = The buffer is used to receive data.
27 FFEW R/W 0h
FIFO enabled for transmit: Only one channel can have this bit field
set.
0h = The buffer is not used to transmit data.
1h = The buffer is used to transmit data.
26-21 RESERVED R 0h

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