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Register Description
147
SWRU543–January 2019
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Direct Memory Access (DMA)
4.3.4.15 DMA_PRIOSET Register (offset = 38h) [reset = 0h]
DMA_PRIOSET is shown in Figure 4-21 and described in Table 4-25.
Each bit of this register represents the corresponding DMA channel. Setting a bit configures the DMA
channel to have a high priority level. Reading the register returns the status of the channel priority mask.
Figure 4-21. DMA_PRIOSET Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SET_n
W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 4-25. DMA_PRIOSET Register Field Descriptions
Bit Field Type Reset Description
31-0 SET_n W 0h
Channel [n] Priority Set
0h = DMA channel [n] is using the default priority level
1h = DMA channel [n] is using the high priority level
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