ADC_MODULE Registers
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SWRU543–January 2019
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Analog-to-Digital Converter (ADC)
13.4.1.10 ADC_DMA_MODE_EN Register (offset = 64h) [reset = 0h]
ADC_DMA_MODE_EN is shown in Figure 13-12 and described in Table 13-12.
Figure 13-12. ADC_DMA_MODE_EN Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED DMA_MODEENABLE
R-0h R/W-0h
Table 13-12. ADC_DMA_MODE_EN Register Field Descriptions
Bit Field Type Reset Description
31-8 RESERVED R 0h
7-0 DMA_MODEENABLE R/W 0h
This register enables DMA mode.
Bit 0: Channel 0 DMA mode enable
Bit 1: Reserved for internal channel
Bit 2: Channel 2 DMA mode enable
Bit 3: Reserved for internal channel
Bit 4: Channel 4 DMA mode enable
Bit 5: Reserved for internal channel
Bit 6: Channel 6 DMA mode enable
Bit 7: Reserved for internal channel
0h = Only the interrupt mode is enabled.
1h = Respective ADC channel is enabled for DMA.