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AES Registers
637
SWRU543–January 2019
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Advance Encryption Standard Accelerator (AES)
17.4.9 AES_KEY1_6 Register (Offset = 20h) [reset = 0h]
AES_KEY1_6 is shown in Figure 17-22 and described in Table 17-12.
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Key (LSW for 256-bit key)
Figure 17-22. AES_KEY1_6 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 17-12. AES_KEY1_6 Register Field Descriptions
Bit Field Type Reset Description
31-0 KEY R/W 0h
Key data
17.4.10 AES_KEY1_7 Register (Offset = 24h) [reset = 0h]
AES_KEY1_7 is shown in Figure 17-23 and described in Table 17-13.
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Key (MSW for 256-bit key)
Figure 17-23. AES_KEY1_7 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 17-13. AES_KEY1_7 Register Field Descriptions
Bit Field Type Reset Description
31-0 KEY R/W 0h
Key data