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Functional Description
59
SWRU543–January 2019
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Copyright © 2019, Texas Instruments Incorporated
Cortex
®
-M4 Processor
Table 2-4. Memory Map
Start Address End Address Description Comment
0x0000.0000 0x0007.FFFF On-chip ROM (Bootloader + DriverLib)
0x0100.0000 0x010F.FFFF Flash
0x2000.0000 0x2003.FFFF Bit-banded on-chip SRAM
0x2200.0000 0x23FF.FFFF Bit-band alias of 0x2000.0000 to 0x200F.FFFF
0x4000.0000 0x4000.0FFF Watchdog timer A0
0x4000.4000 0x4000.4FFF GPIO port A0
0x4000.5000 0x4000.5FFF GPIO port A1
0x4000.6000 0x4000.6FFF GPIO port A2
0x4000.7000 0x4000.7FFF GPIO port A3
0x4000.C000 0x4000.CFFF UART A0
0x4000.D000 0x4000.DFFF UART A1
0x4002.0000 0x4002.07FF I
2
C A0 (master)
0x4002.0800 0x4002.0FFF I
2
C A0 (slave)
0x4002.4000 0x4002.4FFF GPIO port A4
0x4003.0000 0x4003.0FFF General-purpose timer A0
0x4003.1000 0x4003.1FFF General-purpose timer A1
0x4003.2000 0x4003.2FFF General-purpose timer A2
0x4003.3000 0x4003.3FFF General-purpose timer A3
0x400F.7000 0x400F.7FFF Configuration registers
0x400F.E000 0x400F.EFFF System control
0x400F.F000 0x400F.FFFF µDMA
0x4200.0000 0x43FF.FFFF Bit-band alias of 0x4000.0000 to 0x400F.FFFF
0x4401.0000 0x4401.0FFF SD Host (master)
0x4401.8000 0x4401.8FFF Camera Interface
0x4401.C000 0x4401.EFFF I2S (also called McASP)
0x4402.0000 0x4402.0FFF FlashSPI
Used for external serial
flash
0x4402.1000 0x4402.1FFF GSPI (also called APSPI)
Used by application
processor
0x4402.2000 0x4402.2FFF Link SPI (APPS to NWP SPI)
0x4402.5000 0x4402.5FFF MCU reset clock manager
0x4402.6000 0x4402.6FFF MCU configuration space
0x4402.E800 0x4402.E8B8 ADC
0xE000.0000 0xE000.0FFF Instrumentation trace macrocell (ITM)
0xE000.1000 0xE000.1FFF Data watchpoint and trace (DWT)
0xE000.2000 0xE000.2FFF Flash patch and breakpoint (FPB)
0xE000.E000 0xE000.EFFF Cortex-M4 peripherals (NVIC, SysTick,SCB)
0xE004.0000 0xE004.0FFF Trace port interface unit (TPIU)
0xE004.1000 0xE004.1FFF Reserved for embedded trace macrocell (ETM)
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