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Functional Description
309
SWRU543–January 2019
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Copyright © 2019, Texas Instruments Incorporated
General-Purpose Timers
9.3.2 Timer Modes
This section describes the operation of the various timer modes. When using Timer A and Timer B in
concatenated mode, only the Timer A control and status bits must be used; there is no need to use Timer
B control and status bits. The GPTM is placed into individual/split mode by writing a value of 0x4 to the
GPTM Configuration (GPTMCFG) register. In the following sections, the variable n is used in bit field and
register names to imply either a Timer A function or a Timer B function. Throughout this section, the time-
out event in down-count mode is 0x0; the time-out event in up-count mode is the value in the GPTM Timer
n Interval Load (GPTMTnILR) and the optional GPTM Timer n Prescale (GPTMTnPR) registers.
9.3.2.1 One-Shot or Periodic Timer Mode
The selection of one-shot or periodic mode is determined by the value written to the TnMR field of the
GPTM Timer n Mode (GPTMTnMR) register. The timer is configured to count up or down using the
TnCDIR bit in the GPTMTnMR register.
When software sets the TnEN bit in the GPTM Control (GPTMCTL) register, the timer begins counting up
from 0x0 or down from its preloaded value. Table 9-3 lists the values loaded into the timer registers when
the timer is enabled.
Table 9-3. Counter Values When the Timer is Enabled in Periodic or One-Shot Modes
Register Count Down Mode Count Up Mode
GPTMTnR GPTMTnILR 0x0
GPTMTnV
GPTMTnILR in concatenated mode;
GPTMTnPR in combination with
GPTMTnILR in individual mode.
0x0
GPTMTnPS
GPTMTnPR in individual mode; not
available in concatenated mode.
0x0 in individual mode; not available in
concatenated mode.
When the timer is counting down and it reaches the time-out event (0x0), the timer reloads its start value
from the GPTMTnILR and the GPTMTnPR registers on the next cycle. When the timer is counting up and
it reaches the time-out event (the value in the GPTMTnILR and the optional GPTMTnPR registers), the
timer reloads with 0x0. If configured as a one-shot timer, the timer stops counting and clears the TnEN bit
in the GPTMCTL register. If the timer is configured as a periodic timer, it starts counting again on the next
cycle.
In periodic, snap-shot mode, the TnMR field is 0x2 and the TnSNAPS bit is set in the GPTMTnMR
register, the value of the timer at the time-out event is loaded into the GPTMTnR register, and the value of
the prescaler is loaded into the GPTMTnPS register. The free-running counter value is shown in the
GPTMTnV register. In this manner, software can determine the time elapsed from the interrupt assertion
to the ISR entry by examining the snapshot values and the current value of the free-running timer.
Snapshot mode is not available when the timer is configured in one-shot mode.
In addition to reloading the count value, the GPTM can generate interrupts, CCP outputs, and triggers
when it reaches the time-out event. The GPTM sets the TnTORIS bit in the GPTM Raw Interrupt Status
(GPTMRIS) register, and holds it until it is cleared by writing the GPTM Interrupt Clear (GPTMICR)
register. If the time-out interrupt is enabled in the GPTM Interrupt Mask (GPTMIMR) register, the GPTM
also sets the TnTOMIS bit in the GPTM Masked Interrupt Status (GPTMMIS) register. The time-out
interrupt can be disabled by setting the TACINTD bit in the GPTM Timer n Mode (GPTMTnMR) register. In
this case, the TnTORIS bit is not set in the GPTMRIS register.
By setting the TnMIE bit in the GPTMTnMR register, an interrupt condition can also be generated when
the timer value equals the value loaded into the GPTM Timer n Match (GPTMTnMATCHR) and GPTM
Timer n Prescale Match (GPTMTnPMR) registers. This interrupt has the same status, masking, and
clearing functions as the time-out interrupt, but uses the match interrupt bits instead (for example, the raw
interrupt status is monitored using the TnMRIS bit in the GPTM Raw Interrupt Status [GPTMRIS] register).
The interrupt status bits are not updated by the hardware unless the TnMIE bit in the GPTMTnMR register
is set, which is different from the behavior for the time-out interrupt. The µDMA trigger is enabled by
configuring and enabling the appropriate µDMA channel, as well as the type of trigger enable in the GPTM
DMA Event (GPTMDMAEV) register.
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