www.ti.com
CRC Registers
759
SWRU543–January 2019
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Cyclical Redundancy Check (CRC)
20.3.2 CRCSEED Register (Offset = C10h) [reset = 0h]
CRCSEED is shown in Figure 20-2 and described in Table 20-5.
Return to Summary Table.
The CRC SEED/Context (CRCSEED) register is initially written with one of the following three values,
depending on the encoding of the INIT field in the CRCCTRL register:
• The context value written to the CRCSEED register. This encoding is for SEED values from a previous
CRC calculation or a specific protocol. (INIT=0x0)
• 0x0000.0000 (INIT=0x2)
• 0x1111.1111 (INIT=0x3)
Figure 20-2. CRCSEED Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SEED
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 20-5. CRCSEED Register Field Descriptions
Bit Field Type Reset Description
31-0 SEED R/W 0h
SEED/Context Value
This register contains the starting seed of the CRC and checksum
operation. This register also holds the latest result of CRC or
checksum operation.