Texas Instruments CC3235 SimpleLink Series - I2 CSICR Register; I2 CSICR Register Field Descriptions

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SWRU543–January 2019
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Inter-Integrated Circuit (I
2
C) Interface
7.3.20 I2CSICR Register (Offset = 818h) [reset = 0h]
I2CSICR is shown in Figure 7-33 and described in Table 7-24.
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This register clears the raw interrupt. A read of this register returns no meaningful data.
Figure 7-33. I2CSICR Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED RXFFIC
R-0h W-0h
7 6 5 4 3 2 1 0
TXFEIC RXIC TXIC DMATXIC DMARXIC STOPIC STARTIC DATAIC
W-0h W-0h W-0h W-0h W-0h W-0h W-0h W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 7-24. I2CSICR Register Field Descriptions
Bit Field Type Reset Description
31-9 RESERVED R 0h
8 RXFFIC W 0h
Receive FIFO Full Interrupt Mask
Writing a 1 to this bit clears the RXFFIS bit in the I2CSRIS register
and the RXFFMIS bit in the I2CSMIS register.
A read of this register returns no meaningful data.
7 TXFEIC W 0h
Transmit FIFO Empty Interrupt Mask
Writing a 1 to this bit clears the TXFERIS bit in the I2CSRIS register
and the TXFEMIS bit in the I2CSMIS register.
A read of this register returns no meaningful data.
6 RXIC W 0h
Receive Request Interrupt Mask
Writing a 1 to this bit clears the RXRIS bit in the I2CSRIS register
and the RXMIS bit in the I2CSMIS register.
A read of this register returns no meaningful data.
5 TXIC W 0h
Transmit Request Interrupt Mask
Writing a 1 to this bit clears the TXRIS bit in the I2CSRIS register
and the TXMIS bit in the I2CSMIS register.
A read of this register returns no meaningful data.
4 DMATXIC W 0h
Transmit DMA Interrupt Clear
Writing a 1 to this bit clears the DMATXRIS bit in the I2CSRIS
register and the DMATXMIS bit in the I2CSMIS register.
A read of this register returns no meaningful data.
3 DMARXIC W 0h
Receive DMA Interrupt Clear
Writing a 1 to this bit clears the DMARXRIS bit in the I2CSRIS
register and the DMARXMIS bit in the I2CSMIS register.
A read of this register returns no meaningful data.
2 STOPIC W 0h
Receive DMA Interrupt Clear
Writing a 1 to this bit clears the DMARXRIS bit in the I2CSRIS
register and the DMARXMIS bit in the I2CSMIS register.
A read of this register returns no meaningful data.