Texas Instruments CC3235 SimpleLink Series - DMA_USEBURSTSET Register; DMA_USEBURSTSET Register Field Descriptions

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SWRU543–January 2019
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Direct Memory Access (DMA)
4.3.4.7 DMA_USEBURSTSET Register (offset = 18h) [reset = 0h]
DMA_USEBURSTSET is shown in Figure 4-13 and described in Table 4-17.
Each bit of this register represents the corresponding DMA channel. Setting a bit disables the channel's
single request input from generating requests, configuring the channel to only accept burst requests.
Reading the register returns the status of USEBURST. If the amount of data to transfer is a multiple of the
arbitration (burst) size, the corresponding SET[n] bit is cleared after completing the final transfer. If there
are fewer items remaining to transfer than the arbitration (burst) size, the DMA controller automatically
clears the corresponding SET[n ] bit, allowing the remaining items to transfer using single requests. In
order to resume transfers using burst requests, the corresponding bit must be set again. A bit should not
be set if the corresponding peripheral does not support the burst request model.
Figure 4-13. DMA_USEBURSTSET Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SET_n
W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 4-17. DMA_USEBURSTSET Register Field Descriptions
Bit Field Type Reset Description
31-0 SET_n W 0h Channel [n] Useburst Set Bit 0 corresponds to channel 0.
This bit is automatically cleared as described above.
A bit can also be manually cleared by setting the corresponding
CLR[n] bit in the DMAUSEBURSTCLR register.
0h = DMA channel [n] responds to single or burst requests.
1h = DMA channel [n] responds only to burst requests