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DES Registers
677
SWRU543–January 2019
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Data Encryption Standard Accelerator (DES)
18.5.4 DTHE_DES_IC Register (Offset = 83Ch) [reset = 0h]
DTHE_DES_IC is shown in Figure 18-11 and described in Table 18-11.
Return to Summary Table.
Interrupt Acknowledge register. Writing 1 to these bits clears the status flag in the IRIS and IMIS registers.
Always reads zero.
Figure 18-11. DTHE_DES_IC Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED Dout Din RESERVED Cin
R-0h R-0h R-0h R-0h R-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 18-11. DTHE_DES_IC Register Field Descriptions
Bit Field Type Reset Description
31-4 RESERVED R 0h
3 Dout R 0h
Clear “output data movement done” flag.
2 Din R 0h
Clear “input data movement done” flag.
1 RESERVED R 0h
0 Cin R 0h
Clear “context input done” flag.
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