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Peripheral Library APIs for I2S Configuration
411
SWRU543–January 2019
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Copyright © 2019, Texas Instruments Incorporated
Inter-Integrated Sound (I2S) Multichannel Audio Serial Port
12.4.3.5 void I2SIntUnregister (unsigned long ulBase)
Unregisters an interrupt handler for a I2S interrupt.
Parameters:
ulBase — the base address of the I2S module
This function unregisters the interrupt handler. The function clears the handler to be called when an I2S
interrupt occurs. This function also masks off the interrupt in the interrupt controller so that the interrupt
handler no longer is called.
See IntRegister() for information about registering interrupt handlers.
Returns:
None
12.4.3.6 void I2SIntClear (unsigned long ulBase, unsigned long ulStatFlags)
Clears I2S interrupt sources.
Parameters:
ulBase — the base address of the I2S module
ulStatFlags — a bit mask of the interrupt sources to be cleared
The specified I2S interrupt sources are cleared, so that they no longer assert. This function must be called
in the interrupt handler to keep the interrupt from being recognized again immediately upon exit.
The ulIntFlags parameter is the logical OR of any value described in
I2SIntStatus().
Returns:
None
12.4.3.7 Values that can be Passed to I2SIntEnable() and I2SIntDisable() as the ulIntFlags Parameter
Table 12-1 lists the values that can be passed to I2SIntEnable() and I2SIntDisable() as the
ulIntFlags parameter.
Table 12-1. ulIntFlags Parameter
Tag Value Description
I2S_INT_XUNDR 0x00000001 Transmit underrun interrupt enable bit
I2S_INT_XSYNCERR 0x00000002 Unexpected transmit frame-sync interrupt enable bit
I2S_INT_XLAST 0x00000010 Transmit last slot interrupt enable bit
I2S_INT_XDATA 0x00000020 Transmit data ready interrupt enable bit
I2S_INT_XSTAFRM 0x00000080 Transmit start of frame interrupt enable bit
I2S_INT_XDMA 0x80000000
I2S_INT_ROVRN 0x00010000 Receiver overrun interrupt enable bit
I2S_INT_RSYNCERR 0x00020000 Unexpected receive frame-sync interrupt enable bit
I2S_INT_RLAST 0x00100000 Receive start of frame interrupt enable bit
I2S_INT_RDATA 0x00200000 Receive data ready interrupt enable bit
I2S_INT_RSTAFRM 0x00800000 Receive start of frame interrupt enable bit
I2S_INT_RDMA 0x40000000