Texas Instruments CC3235 SimpleLink Series - GPIOMIS Register; GPIOMIS Register Field Descriptions

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SWRU543–January 2019
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General-Purpose Input/Outputs (GPIOs)
5.5.8 GPIOMIS Register (offset = 418h) [reset = 0h]
GPIOMIS is shown in Figure 5-11 and described in Table 5-11.
The GPIOMIS register is the masked interrupt status register. If a bit is set in this register, the
corresponding interrupt has triggered an interrupt to the interrupt controller. If a bit is clear, either no
interrupt has been generated, or the interrupt is masked.
GPIOMIS is the state of the interrupt after masking.
Figure 5-11. GPIOMIS Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED MIS
R-0h R-0h
Table 5-11. GPIOMIS Register Field Descriptions
Bit Field Type Reset Description
31-8 RESERVED R 0h
7-0 MIS R 0h
GPIO Masked Interrupt Status
For edge-detect interrupts, this bit is cleared by writing a 1 to the
corresponding bit in the GPIOICR register. For a GPIO level-detect
interrupt, the bit is cleared when the level is deasserted.
0h = An interrupt condition on the corresponding pin is masked or
has not occurred.
1h = An interrupt condition on the corresponding pin has triggered an
interrupt to the interrupt controller.