Texas Instruments CC3235 SimpleLink Series - GPIOICR Register; GPIOICR Register Field Descriptions

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SWRU543–January 2019
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General-Purpose Input/Outputs (GPIOs)
5.5.9 GPIOICR Register (offset = 41Ch) [reset = 0h]
GPIOICR is shown in Figure 5-12 and described in Table 5-12.
The GPIOICR register is the interrupt clear register. For edge-detect interrupts, writing 1 to the IC bit in the
GPIOICR register clears the corresponding bit in the GPIORIS and GPIOMIS registers. If the interrupt is a
level-detect, the IC bit in this register has no effect. In addition, writing 0 to any of the bits in the GPIOICR
register has no effect.
Figure 5-12. GPIOICR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED IC
R-0h W1C-0h
Table 5-12. GPIOICR Register Field Descriptions
Bit Field Type Reset Description
31-8 RESERVED R 0h
7-0 IC W1C 0h
GPIO Interrupt Clear
0h = The corresponding interrupt is unaffected.
1h = The corresponding interrupt is cleared.