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SWRU543–January 2019
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Direct Memory Access (DMA)
4.3.4.23 DMA_PV Register (offset = FB0h) [reset = 200h]
DMA_PV is shown in Figure 4-29 and described in Table 4-33.
Indicate the version number of peripheral.
Figure 4-29. DMA_PV Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED MAJVER MINVER
R-0h R-2h R-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 4-33. DMA_PV Register Field Descriptions
Bit Field Type Reset Description
31-16 RESERVED R 0h
15-8 MAJVER R 2h
Major Version
7-0 MINVER R 0h
Minor Version
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