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I2C Registers
229
SWRU543–January 2019
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Inter-Integrated Circuit (I
2
C) Interface
7.3.3 I2CMDR Register (Offset = 8h) [reset = 0h]
I2CMDR is shown in Figure 7-16 and described in Table 7-7.
Return to Summary Table.
This register contains the data to be transmitted when in the master transmit state and the data received
when in the master receive state. If the BURST bit is enabled in the I2CMCS register, then the
I2CFIFODATA register is used for the current data transmit or receive value and this register is ignored.
NOTE: This register is read-sensitive. See the register description for details.
Figure 7-16. I2CMDR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED DATA
R-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 7-7. I2CMDR Register Field Descriptions
Bit Field Type Reset Description
31-8 RESERVED R 0h
7-0 DATA R/W 0h
This byte contains the data transferred during a transaction.
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