Full
Empty
LH or DMA Read
Core Write
.
<MCSPI_IRQSTATUS[TiE]>*
* non-DMA mode only. In DMA mode, the DMA TX request is asserted
to its active level under identical conditions.
<MCSPI_XFERLEVEL[AFL]>
(in bytes)
Full
Empty
LH or DMA Read
Core Write
.
<MCSPI_IRQSTATUS[RiF]>*
* non-DMA mode only. In DMA mode, the DMA RX request is asserted
to its active level under identical conditions.
<MCSPI_XFERLEVEL[AFL]>
(in bytes)
Functional Description
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SWRU543–January 2019
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SPI (Serial Peripheral Interface)
8.2.3.4.1.2 Buffer Almost Full
The bit field MCSPI_XFERLEVEL[AFL] is required when the buffer is used to receive a SPI word from a
slave (MCSPI_CHCONF[FFER] [FFRE]? See figs. 6 to 9. must be set to 1), and defines the Almost Full
buffer status. See Figure 8-11.
When the FIFO pointer reaches this level, an interrupt or a DMA request is sent to the local host to enable
the system to read AFL+1 bytes from the receive register. AFL+1 must correspond to a multiple value of
MCSPI_CHCONF[WL]. When DMA is used, the request is deasserted after the first receive register read.
No new request is asserted until it has performed the correct number of read accesses.
Figure 8-11. Buffer Almost Full Level (AFL)
8.2.3.4.1.3 Buffer Almost Empty
The bit field MCSPI_XFERLEVEL[AEL] is required when the buffer is used to transmit a SPI word to a
slave (MCSPI_CHCONF[FFEW] must be set to 1), and defines the Almost Empty buffer status.
When the FIFO pointer has reached this level, an interrupt or a DMA request is sent to the local host to
enable the system to write AEL+1 bytes to the transmit register. AEL+1 must correspond to a multiple
value of MCSPI_CHCONF[WL]. When DMA is used, the request is deasserted after the first transmit
register write. No new request is asserted again until the system has performed the right number of write
accesses. See Figure 8-12.
Figure 8-12. Buffer Almost Empty Level (AEL)
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