DES Registers
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SWRU543–January 2019
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Data Encryption Standard Accelerator (DES)
18.5.13 DES_CTRL Register (Offset = 1020h) [reset = 80000000h]
DES_CTRL is shown in Figure 18-20 and described in Table 18-20.
Return to Summary Table.
Figure 18-20. DES_CTRL Register
31 30 29 28 27 26 25 24
CONTEXT RESERVED
RO-1h RO-0h
23 22 21 20 19 18 17 16
RESERVED
RO-0h
15 14 13 12 11 10 9 8
RESERVED
RO-0h
7 6 5 4 3 2 1 0
RESERVED MODE TDES DIRECTION INPUT_READY OUTPUT_REA
DY
RO-0h R/W-0h R/W-0h R/W-0h RO-0h RO-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 18-20. DES_CTRL Register Field Descriptions
Bit Field Type Reset Description
31 CONTEXT RO 1h
If 1, this read-only status bit indicates that the context data registers
can be overwritten and the host is permitted to write the next
context.
30-6 RESERVED RO 0h
5-4 MODE R/W 0h
Select CBC, ECB or CFB mode.
0h = ECB mode
1h = CBC mode
2h = CFB mode
3h = Reserved
3 TDES R/W 0h
Select DES or triple DES encryption or decryption.
0h = DES mode
1h = TDES mode
2 DIRECTION R/W 0h
Select encryption or decryption.
0h = Decryption is selected
1h = Encryption is selected
1 INPUT_READY RO 0h
When 1, ready to encrypt or decrypt data.
0 OUTPUT_READY RO 0h
When 1, data decrypted or encrypted ready.
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