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SHA/MD5 Functional Description
695
SWRU543–January 2019
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SHA/MD5 Accelerator
19.1.1.3 Hash Core Control
When the hash core is idle or done, a new hash operation can be started. Any additional information
needed by the hash core (mode of operation, data to process, input digest, if not starting from algorithm
constants or continuing) must be provided by programming the SHA registers before the core can accept
the operation.
19.1.1.4 Host Interface Bank
The host interface bank can access the hash core for hashing individual 64-byte hash blocks. The host
interface bank contains registers such as the data FIFO (SHA Data n Input [SHAMD5_DATA_n_IN]
registers), the SHA Inner Digest x (SHAMD5_IDIGEST_X) registers, and several control and status
registers.
The host interface block contains all relevant control logic for performing hash and HMAC computations
on large (that is, larger than one hash block) blocks of data, including hash padding, final hash, and outer
hash. The block provides the necessary flow control to the SHA µDMA and interrupt interface.
19.1.2 µDMA and Interrupt Requests
The SHA/MD5 module can operate in µDMA mode, where the module can assert a µDMA request for
context in, context out, or data input. The µDMA signals that can be generated are:
• Context In µDMA request: Request for key, digest, mode, and LENGTH information
• Context Out µDMA request: Request for read from HMAC
• Data In µDMA request: Request input data in multiples of 16 bytes
The SHA/MD5 module be programmed to assert an interrupt when the µDMA has completed its last
transfer, by programming the SHA DMA Interrupt Mask (DTHE_SHA_IM) register. The SHA DMA Raw
Interrupt Status (DTHE_SHA_RIS) register, at CCM offset 0x014, indicates when the µDMA has
completed, and can be cleared by the SHA DMA Interrupt Clear (DTHE_SHA_IC) register.
If context and data transfers are to be handled through software in interrupt mode, then the SHA Interrupt
Enable (SHAMD5_IRQENABLE) register can be used to enable interrupt triggering when context out,
context in, data in, or data out is ready. The SHA Interrupt Status (SHAMD5_IRQSTATUS) register
indicates when an interrupt is triggered. Table 19-1 lists interrupts and events.
NOTE: If the application uses interrupt mode, an interrupt is generated for each block of processed
data. To support larger data flow, µDMA mode should be used and the bits in the
SHAMD5_IRQENABLE register should be cleared.
Table 19-1. Interrupts and Events
Event Description
SHAMD5_IRQSTATUS[3]: CONTEXT_OUT Context output interrupt
SHAMD5_IRQSTATUS[1]: DATA_IN Data input interrupt
SHAMD5_IRQSTATUS[0]: CONTEXT_IN Context input interrupt
19.1.3 Operation Description
The SHA/MD5 module can run the SHA-1, SHA-224, SHA-256, and MD5 algorithms, depending on the
value of the ALGO bit field in the SHA Mode (SHAMD5_MODE) register. See Table 19-2.
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