Texas Instruments CC3235 SimpleLink Series - CC_IRQSTATUS Register Field Descriptions

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SWRU543–January 2019
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Parallel Camera Interface Module
Table 14-6. CC_IRQSTATUS Register Field Descriptions (continued)
Bit Field Type Reset Description
10 FW_ERR_IRQ R/W 0h
Frame Height Error
0h (W) = Event status bit unchanged
0h (R) = Event false
1h (W) = Event status bit is reset
1h (R) = Event is true ("pending")
9 FSC_ERR_IRQ R/W 0h
False Synchronization Code
0h (W) = Event status bit unchanged
0h (R) = Event false
1h (W) = Event status bit is reset
1h (R) = Event is true ("pending")
8 SSC_ERR_IRQ R/W 0h
Shifted Synchronization Code
0h (W) = Event status bit unchanged
0h (R) = Event false
1h (W) = Event status bit is reset
1h (R) = Event is true ("pending")
7-5 RESERVED R/W 0h
4 FIFO_NOEMPTY_IRQ R/W 0h
FIFO is not empty
0h (W) = Event status bit unchanged
0h (R) = Event false
1h (W) = Event status bit is reset
1h (R) = Event is true ("pending")
3 FIFO_FULL_IRQ R/W 0h
FIFO is full
0h (W) = Event status bit unchanged
0h (R) = Event false
1h (W) = Event status bit is reset
1h (R) = Event is true ("pending")
2 FIFO_THR_IRQ R/W 0h
FIFO threshold has been reached
0h (W) = Event status bit unchanged
0h (R) = Event false
1h (W) = Event status bit is reset
1h (R) = Event is true ("pending")
1 FIFO_OF_IRQ R/W 0h
FIFO overflow has occurred
0h (W) = Event status bit unchanged
0h (R) = Event false
1h (W) = Event status bit is reset
1h (R) = Event is true ("pending")
0 FIFO_UF_IRQ R/W 0h
FIFO underflow has occurred
0h (W) = Event status bit unchanged
0h (R) = Event false
1h (W) = Event status bit is reset
1h (R) = Event is true ("pending")