ADC_MODULE Registers
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SWRU543–January 2019
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Analog-to-Digital Converter (ADC)
13.4.1.21 ADC_CH_ENABLE Register (offset = B8h) [reset = 0h]
ADC_CH_ENABLE is shown in Figure 13-23 and described in Table 13-23.
Figure 13-23. ADC_CH_ENABLE Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED EXTERNAL_CH_GATE RESERVED
R-0h R/W-0h R-0h
Table 13-23. ADC_CH_ENABLE Register Field Descriptions
Bit Field Type Reset Description
31-5 RESERVED R 0h
4-1 EXTERNAL_CH_GATE R/W 0h
Bits[4:1]: control ADC channel isolation switches. By default, all
channel analog inputs are isolated (value: 0).
Bit1: 1 connects channel 0 to pin 57 (ADC_CH0)
Bit2: 1 connects channel 2 to pin 58 (ADC_CH1)
Bit3: 1 connects channel 4 to pin 59 (ADC_CH2)
Bit4: 1 connects channel 6 to pin 60 (ADC_CH3)
0 RESERVED R 0h
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