Texas Instruments CC3235 SimpleLink Series - AES_C_LENGTH_0 Register; AES_C_LENGTH_0 Register Field Descriptions

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SWRU543–January 2019
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Advance Encryption Standard Accelerator (AES)
17.4.22 AES_C_LENGTH_0 Register (Offset = 54h) [reset = 0h]
AES_C_LENGTH_0 is shown in Figure 17-35 and described in Table 17-25.
Return to Summary Table.
Crypto data length registers (LSW and MSW) store the cryptographic data length in bytes for all modes.
Once processing with this context is started, this length decrements to zero. Data lengths up to (2
61
– 1)
bytes are allowed.
For GCM, any value up to 2
36
– 32 bytes can be used. This is because a 32-bit counter mode is used; the
maximum number of 128-bit blocks is 2
32
– 2, resulting in a maximum number of bytes of 2
36
– 32.
A write to this register triggers the engine to start using this context. This is valid for all modes except
GCM and CCM.
For the combined modes, this length does not include the authentication-only data; the authentication
length is specified in the AES_AUTH_LENGTH register below.
All modes must have a length > 0. For the combined modes, it is allowed to have one of the lengths equal
to zero.
For the basic encryption modes (ECB/CBC/CTR/ICM/CFB128) it is allowed to program zero to the length
field; in that case the length is assumed infinite.
All data must be byte (8-bit) aligned; bit aligned data streams are not supported by the AES Engine.
For a host read operation, these registers return all-zeroes.
Figure 17-35. AES_C_LENGTH_0 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LENGTH
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 17-25. AES_C_LENGTH_0 Register Field Descriptions
Bit Field Type Reset Description
31-0 LENGTH R/W 0h
Data length (LSW)