SPI Registers
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SWRU543–January 2019
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SPI (Serial Peripheral Interface)
8.6.9 SPI_TX Register (offset = 138h) [reset = 0h]
SPI_TX is shown in Figure 8-28 and described in Table 8-15.
This register contains a single SPI word to transmit on the serial link, depending on SPI word length. See
Chapter Access to data registers for the list of supported accesses; the little-endian host accesses the SPI
8-bit word on 0x00, while the big-endian host accesses it on 0x03.
Figure 8-28. SPI_TX Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDATA
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 8-15. SPI_TX Register Field Descriptions
Bit Field Type Reset Description
31-0 TDATA R/W 0h
Channel data to transmit
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