Texas Instruments CC3235 SimpleLink Series - I2 CMICR Register; I2 CMICR Register Field Descriptions

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SWRU543–January 2019
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Inter-Integrated Circuit (I
2
C) Interface
7.3.8 I2CMICR Register (Offset = 1Ch) [reset = 0h]
I2CMICR is shown in Figure 7-21 and described in Table 7-12.
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This register clears the raw and masked interrupts.
Figure 7-21. I2CMICR Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED RXFFIC TXFEIC RXIC TXIC
R-0h W-0h W-0h W-0h W-0h
7 6 5 4 3 2 1 0
ARBLOSTIC STOPIC STARTIC NACKIC DMATXIC DMARXIC CLKCIC IC
W-0h W-0h W-0h W-0h W-0h W-0h W-0h W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 7-12. I2CMICR Register Field Descriptions
Bit Field Type Reset Description
31-12 RESERVED R 0h
11 RXFFIC W 0h
Receive FIFO Full Interrupt Clear
Writing a 1 to this bit clears the RXFFIS bit in the I2CMRIS register
and the RXFFMIS bit in the I2CMMIS register.
A read of this register returns no meaningful data.
10 TXFEIC W 0h
Transmit FIFO Empty Interrupt Clear
Writing a 1 to this bit clears the TXFERIS bit in the I2CMRIS register
and the TXFEMIS bit in the I2CMMIS register.
A read of this register returns no meaningful data.
9 RXIC W 0h
Receive FIFO Request Interrupt Clear
Writing a 1 to this bit clears the RXRIS bit in the I2CMRIS register
and the RXMIS bit in the I2CMMIS register.
A read of this register returns no meaningful data.
8 TXIC W 0h
Transmit FIFO Request Interrupt Clear
Writing a 1 to this bit clears the TXRIS bit in the I2CMRIS register
and the TXMIS bit in the I2CMMIS register.
A read of this register returns no meaningful data.
7 ARBLOSTIC W 0h
Arbitration Lost Interrupt Clear
Writing a 1 to this bit clears the ARBLOSTRIS bit in the I2CMRIS
register and the ARBLOSTMIS bit in the I2CMMIS register.
A read of this register returns no meaningful data.
6 STOPIC W 0h
STOP Detection Interrupt Clear
Writing a 1 to this bit clears the STOPRIS bit in the I2CMRIS register
and the STOPMIS bit in the I2CMMIS register.
A read of this register returns no meaningful data.
5 STARTIC W 0h
START Detection Interrupt Clear
Writing a 1 to this bit clears the STARTRIS bit in the I2CMRIS
register and the STARTMIS bit in the I2CMMIS register.
A read of this register returns no meaningful data.